HomeTechnologyHigh Performance ComputingVishay Intertechnology Space-Saving 60 A VRPower Smart Power Stages Increase Accuracy While Simplifying...

Vishay Intertechnology Space-Saving 60 A VRPower Smart Power Stages Increase Accuracy While Simplifying Designs

For Telecom Equipment and Datacenter Servers, Devices Feature Integrated Current and Temperature Monitors in PowerPAK MLP55-32L Package

Meeting the need for real-time processor and memory power consumption monitoring in high-performance telecom equipment and datacenter servers, Vishay Intertechnology, Inc. on November 30, 2016, introduced two new 60 A VRPower smart power stages with integrated current and temperature monitors for multi-phase DC/DC systems. Combining power MOSFETs, an advanced driver IC, and a bootstrap FET in the thermally enhanced low-profile 5 mm by 5 mm by 0.66 mm PowerPAK MLP55-32L / QFN package, the Vishay Siliconix SiC645 and SiC645A simplify designs and deliver higher accuracy than comparable standard DrMOS products while offering a 16 % smaller footprint than similar competing devices.

Unlike solutions that monitor power consumption using inductor DCR sensing — a technique with lower accuracy that requires external components such as a thermistor for temperature compensation — the SiC645 and SiC645A utilize low-side MOSFET RDS(ON) sensing to accurately report current (IMON) and temperature (TMON) using 5 mV/A and 8 mV/C signals, respectively. This method of current sensing is accurate over a wide load range and is internally temperature-compensated, simplifying designs by removing the need for external circuitry. In addition, it eliminates current sense traces while delivering fast performance without noise or external filtering.

The power stages’ improved accuracy meets Intel’s stringent VR13 and VR13.x current monitoring accuracy requirements and allows for better utilization of a server CPU’s turbo boost capability, a critical advantage for datacenter customers requiring improved performance without increasing costs. Light-load efficiency is supported by a dedicated low-side FET control pin.

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