Due to massive pool of specialised VLSI (Very Large Scale Integration) engineers, large number of Global Capability Centre (GCCs) presence and ongoing government support, India currently accounts for nearly 20% of the world’s semiconductor design workforce. This number highlights the India’s increasing role in global chip design and research. The statement of accounting 20% global workforce in semiconductor design was made by S. Krishnan, the MeitY Secretary on the side-lines of SEMICON India 2026 in New Delhi.
The government is prioritising the development of semiconductor design talent, said S. Krishnan. He said an ongoing programme is focused on training around 85,000 semiconductor design engineers, while skill-development efforts are also being expanded across the semiconductor value chain, with a strong focus on supporting semiconductor manufacturing in India.
The semiconductor design workforce will play an important in strengthening India’s position in the global semiconductor ecosystem. According to government data, India holds 7% of the world’s semiconductor-related Global Capability Centres (GCSs) along with Indian engineers continue to contributing to chip design, fabrication, verification and testing activities.
The government is taking action to move beyond design and improve semiconductor ecosystem by covering fabrication, advanced packaging, assembly and testing, semiconductor equipment and materials, research and development (R&D), and talent development. The recent organised event Semicon 2.0 has an outlay of ₹1,27,500 crore and is structured around six pillars which include design, machine, materials, advanced packaging, additional fabs, research, and talent.
There are different schemes supported by the government body encouraging semiconductor design which include Design Linked Incentive (DLI) Scheme and the Chips to Startup (C2S) Programme. The focus of these programmes is to train around 85,000 semiconductor design engineers. The initiatives are also aimed at strengthening India’s domestic chip-design capabilities and building a stronger semiconductor design ecosystem.
