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Achronix Introduces acceleration board for data center applications

QSFP

Achronix Semiconductor Corporation today announced the availability of the new PCIe form factor Accelerator-6D accelerator board which is the industry’s highest single-FPGA memory bandwidth, PCIe add-in card for high-speed data center acceleration applications. The board integrates a Speedster™22i HD1000 FPGA with 700,000 look-up-tables that connects to six independent memory controllers allowing for up to 192 GB of memory and 690 Gbps of total memory bandwidth.

Each DRAM controller on the HD1000 runs at 1,600 MT/s and connects to two SODIMMs allowing for single, dual- and quad-rank SODIMM and SORDIMM DDR3 operation. The board also has four QSFP+ connectors for 10G/40G Ethernet connectivity and supports PCIe Gen3 ×8 operation. The controllers for the DDR3, Ethernet and PCIe interfaces are implemented as embedded hard blocks inside the HD1000 FPGA, which eliminates the requirement to use valuable programmable resources inside the FPGA to implement these functions. In addition, the embedded hard controllers guarantee timing on these complex high-performance interfaces, enabling designers to focus their valuable time on developing data center acceleration applications.

The Accelerator-6D board is the only FPGA-based PCIe board that has 6 independent DRAM memory ports connected to a single FPGA. Each independent port can be configured with up to 32 GB of DDR3 memory. The memory ports combined with the 4 QSFP+ modules that support 4x 40G Ethernet is the perfect platform for data center architects to develop intelligent NIC cards for NFV network acceleration or network security.

“The Accelerator-6D board offers a unique value proposition to the data center, high-performance compute market segment that uses PCIe add-in cards,” said Steve Mensor, Vice President of Marketing, Achronix Semiconductor. “The Accelerator-6D board offers the highest memory bandwidth for an FPGA-based PCIe form factor board, and memory bandwidth is typically the bottleneck of high performance computer systems.”

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