The solution utilises the ARM MBIST interface to reduce the impact of MBIST on critical timing paths to and from memories in functional operation.
Cadence Design Systems’ Modus test solution has enabled support for safety-critical system-on-chip (SoC) designs using the ARM Memory Built-In Self Test (MBIST) interface.
To demonstrate the success of the collaboration, Cadence and ARM have completed silicon validation using an ARM Cortex-A73 processor in conjunction with the Modus test solution’s automatic test pattern generation (ATPG) and diagnostic capabilities.
Through Cadence’s support of the ARM MBIST interface, customers can deliver SoC designs to market faster and with better power, performance and area (PPA). For example, the Modus test solution provides ARM MBIST interface users with the option for programmable memory built-in self test (PMBIST) to use a single bus to service multiple memories with one MBIST controller. The solution utilises the ARM MBIST interface to reduce the impact of MBIST on critical timing paths to and from memories in functional operation and for a higher quality at-speed test. Finally, the Modus test solution provides a physical-to-logical mapping capability, which reduces the need for manual, error-prone work.
“One feature is automation of the physical-to-logical mapping capability that bridges the definition of logical memories to a customer’s unique physical memory configuration, simplifying the task of integrating MBIST for ARM IP in their products,” said Teresa McLaurin, fellow and director, technology services group, ARM.
The Cadence Modus test solution is a comprehensive next-generation physically aware design-for-test (DFT), ATPG and silicon diagnostics tool. Using the Modus test solution, customers can experience up to 3X reduction in test time using its patented physically aware 2D Elastic Compression architecture, without any impact on fault coverage or chip size.
