With the ChipVORX based LAN Test Generator, GOEPEL electronic now offers a tool for automated test of FPGA design based LAN interfaces. The solution can be used for both verification of prototypes and production test. Due to the extremely high level of automation, applications can be created very quickly and effectively.
The LAN Test Generator is included as standard in the JTAG/Boundary Scan software SYSTEM CASCON. It detects FPGA-connected LAN interfaces, identifies the used pins and the download of a standardized IP is initiated and configured according to the IP-to-Pin-Mapping. Thereafter, the actual functional test of the interface is executed with the help of the external PHY. The test serves to prove the basic functionality of the LAN interfaces and on the other hand to identify existing errors. The user can select different test scenarios, ensuring very high fault coverage, including for dynamic errors.
ChipVORX technology requires no FPGA-specific design synthesis or specialized tools and no FPGA development expertise is required. As a result, use of this technology is easy and uncomplicated. On the hardware side, the JTAG/Boundary Scan platform SCANFLEX is supported. The new Test Generator is a standard tool of SYSTEM CASCON from version 4.6.5. For users with an active maintenance contract, the new release is free.
For details visit: www.goepel.com
