In a significant development, Renesas Electronics Corporation, a prominent semiconductor company, has officially introduced a cutting-edge 32-bit CPU core built upon the open-standard RISC-V instruction set architecture (ISA). This latest addition to Renesas’ microcontroller portfolio, known for its RX Family and RA Family based on the Arm Cortex-M architecture, expands the company’s offerings in the rapidly evolving landscape of embedded systems.
The newly developed RISC-V CPU core is versatile, serving as a primary application controller, a secondary core in system-on-chips (SoCs), on-chip subsystems, or within deeply embedded Application-specific Standard Products (ASSPs). Renesas boasts a remarkable performance metric of 3.27 CoreMark/MHz, surpassing comparable architectures. Furthermore, its silicon area implementation enhances cost-effectiveness by minimizing both operating and standby leakage currents.
This CPU core provides customization options through the RV32 ‘I’ or ‘E’ option, allowing optimization based on specific application requirements. Renesas has integrated several RISC-V ISA extensions, including the M extension for optimized multiplication and division operations, the A extension for atomic access instructions, the C extension for compressed instructions to conserve memory space, and the B extension for bit manipulation.
The RISC-V ISA’s flexibility empowers designers to tailor elements according to their unique use cases, optimizing power consumption, performance, and silicon footprint. Notable features include a stack monitor register to detect and prevent stack memory overflows, enhancing the robustness of application software.
In terms of architecture, the CPU includes a dynamic branch prediction unit for efficient code execution, supporting compact Jtag debug interfaces suitable for microcontrollers with limited pins. Additionally, a register bank save function improves response latency and enables real-time behaviour in embedded devices. For enhanced system insights, an instruction tracing unit is available.
Building on its history of innovation, Renesas has previously introduced 32-bit voice-control and motor-control ASSP devices, along with the RZ/Five 64-bit general-purpose microprocessors (MPUs) based on CPU cores developed by Andes Technology Corp. The company is currently in the sampling phase, providing devices based on the new core to select customers. Renesas anticipates launching its inaugural RISC-V-based MCU and accompanying development tools in the first quarter of 2024.
