HomeNewsIndia NewsSiFive Launches Open-Source RISC-V SoC

    SiFive Launches Open-Source RISC-V SoC

    SiFive, a provider of customized, open-source-enabled semiconductors, has announced the availability of its Freedom Everywhere 310 (FE310) system on a chip (SoC), which it says is the industry’s first commercially available SoC based on the free and open RISC-V instruction set architecture, along with the corresponding low-cost HiFive1 software development board.

    As part of this availability, SiFive also has contributed the register-transfer level (RTL) code for FE310 to the open-source community.

    “We started with this revolutionary concept — that instruction sets should be free and open — and were amazed by the incredible rippling effect this has had on the semiconductor industry because it provided a viable alternative to what was previously closed and proprietary,” said Krste Asanovic, co-founder and chief architect, SiFive. “In the few short months since we’ve announced the Freedom Platforms, we’ve seen a tremendous response to our vision of customizable SoCs. The FE310 is a major step forward in the movement toward open-source and mass customization, and SiFive is excited to bring the opportunity for innovation back into the hands of system architects.”

    By contributing the FE310 RTL code to the open-source community, SiFive said it aims to encourage open-source development of both software support for RISC-V as well as other open hardware development. The RTL code also empowers chip designers with the ability to customize their own SoC on top of the base FE310.

    “SiFive has achieved a significant milestone for the RISC-V ecosystem,” said Rick O’Connor, executive director of the not-for-profit RISC-V Foundation. “We are thrilled to see the first commercial silicon based on RISC-V standards come to market and look forward to continued technology leadership from the SiFive team.”

    The FE310 features SiFive’s E31 CPU Coreplex, a 32-bit RV32IMAC core running at 320+ MHz. Additional features include a 16KB L1 Instruction Cache, a 16KB Data SRAM scratchpad, hardware multiply/divide, debug module, one-time programmable non-volatile memory (OTP), flexible clock generation with on-chip oscillators and PLLs, and a wide variety of peripherals including UARTs, QSPI, PWMs and timers. The HiFive1 is an Arduino-Compatible development board featuring the FE310.

    ELE Times Bureau
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