Cadence on September 24, 2026, announced a new agent for the Cadence ChipStack AI Super Agent that automates front-end digital design and verification, covering power, performance and area (PPA)-driven spec-to-RTL generation, RTL analysis and refinement through natural language prompts. Building on the industry’s first agentic workflow for front-end design and verification announced in February 2026, the RTL Generation Agent extends the ChipStack AI Super Agent from autonomous verification and debug to high-quality RTL creation and optimization. In early evaluations, the RTL Generation Agent delivered an average 24% reduction in area and 18% reduction in power compared with pure foundation model code generation, while ensuring 100% functionally accurate RTL, according to Cadence.
Building on the industry’s first agentic workflow for front end design and verification announced in February 2026, this RTL Generation Agent extends the ChipStack AI Super Agent from autonomous verification and debug into high quality RTL creation and optimization.
“These latest agentic AI advancements take us from AI assisted tools to coordinated agentic workflows that behave more like virtual design engineers with expert-level command of the underlying technologies,” said Chin-Chi Teng, senior vice president and general manager in the Digital & Signoff Group at Cadence. “By pairing agentic automation of spec-to-RTL and RTL refinement with our proven implementation and signoff engines, we enable customers to achieve better design outcomes with higher productivity and stronger correlation across the design flow, further extending Cadence’s leadership in AI driven, end to end chip design.”
Cadence’s transformational approach to applying agentic AI to engineering design is founded on a hierarchy of solutions—super agents orchestrate task-specific agents, which in turn use trusted electronic design automation (EDA) software, optimized for agentic workflows. The new RTL Generation Agent converts high level specification into production ready RTL optimized for PPA.
Customer Validation from Honda
Early collaborations with Honda R&D demonstrate how these agentic AI capabilities translate into real world PPA and productivity gains on next generation SoCs.
Honda is evaluating the RTL Generation Agent on advanced automotive SoCs, where safety critical requirements and tight power and cost envelopes demand highly optimized RTL.
“As a key enabler of Software-Defined Vehicles (SDVs), AI technology for autonomous driving is advancing rapidly. However, the long development cycle of SoCs remains a major challenge. With the Cadence ChipStack AI Super Agent’s RTL Generation Agent and AI-powered automation, Honda R&D is working to improve productivity from specification through RTL development,” said Tomoya Nishino, chief engineer and general manager, Digital Engine Development Division, SDV R&D Center, Honda R&D Co., Ltd.
Smarter RTL Updates and Early PPA Insight
In addition to new RTL creation within the RTL Generation Agent, Cadence is introducing technology for design updates to existing RTL based on new requirements. This RTL upgrade flow brings AI automation to accelerate RTL revision, enabling customers to rapidly adapt legacy RTL to new architecture requirements, new PPA targets and new functional requirements. Engineers describe changes at a high level, and the agents carry out the updates while analyzing and verifying PPA and functionality.
Advancing Cadence’s Agentic AI Vision
These enhancements build on Cadence’s “Design for AI and AI for Design” strategy highlighted at CadenceLIVE and Computex, further extending the company’s leadership in AI driven chip design. From the initial ChipStack AI Super Agent launch through June’s announcement of the industry’s first fully autonomous virtual engineer for chip design, and now today’s RTL Generation Agent, Cadence continues to expand the scope of agentic workflows across the design stack. Together with the broader ChipStack, InnoStack and ViraStack AI Super Agent portfolio, they advance a scalable platform that applies AI across digital, analog and verification domains.
