Beyond 300 Layers of Memory
The race to make denser, more-powerful 3D NAND flash memory has led to huge innovation but also new manufacturing challenges. Taller devices-three-hundred-plus layers-could be threatened in yield, performance, and reliability due to constructive-tier bending and material collapse. In this sense, these challenges come from stress mismatches in alternating stacks of silicon nitride (SiN) and oxide (TEOS) layers that constitute this memory structure.
To comprehend and solve the problem, the Semiverse Solutions team used SEMulator3D virtual Design of Experiments (DOE) to replicate, measure, and analyze stress-induced deformation in the fabrication process. The outcomes emphasize the very important consideration of stress management and material properties in realizing manufacturable high-layer-count NAND architectures.
Understanding How 3D NAND Is Built
It achieves higher densities in 3D NAND by stacking SiN and oxide layers vertically in a staircase arrangement. Contacts are etched through such tall stacks to reach underlying transistors, and slit etchings divide the structure into functional memory blocks.
Until SiN can be replaced by conductive metal, an oxide cantilever is temporarily formed: it is anchored at one end while being unsupported at the other end. This rather fragile structure increasingly becomes vulnerable as the number of layers grows, expanding from ~550 nm at 200 layers to ~700 nm at 300 layers. Various contributors to tier collapse are as follows:
- Stress and strain mismatches between SiN and oxide
- Surface tension during SiN removal
- Cantilever length and geometry
What the Virtual Studies Revealed
Using SEMulator3D’s stress analysis tools, the team conducted two DOE studies to characterize how stress may evolve with tier bending and collapse.
Key findings from the first DOE:
- SiN Stiffness (Young’s Modulus, Ey) and oxide thickness are the dominant variables influencing stress-based deformation.
- Present at low Ey values (70 GPa) due to minimal displacement.
- At 125 GPa, collapse occurred at longer cantilever lengths (700 nm), especially with thinner oxides.
- At 256 GPa, severe displacement and voiding occurred across all test conditions.
- Increasing oxide thickness improved resistance but did not eliminate failure risks.
The second DOE compared the effects of intrinsic SiN stress (compressive vs. tensile). Results showed compressive SiN caused larger displacements, widening the range of potential collapse.
The manufacturing implications
These studies present obvious engineer methods that can be employed to maximize yields in ultra-high-layer NAND:
- The SiN and oxide stress values need to be matched and hopefully reduced.
- Shorten cantilever length by designing an etch profile.
- If possible, increase oxide thickness to stabilize the stack.
Through virtual simulation of these interactions, SEMulator3D engineers have the ability to realize the process changes that actually matter without being solely reliant on expensive experimental work on the actual silicon.
Conclusion
With NAND flash closing in on 300 layers and more, tier bending and collapse remain edge manufacturing threats. Stress analyses and virtual DOE studies by the Semiverse team have revealed that exacting control of material properties and stack geometry is key to both securing yields and shortening time to market.
With the SEMulator3D platform from Lam Research, chipmakers gain a powerful predictive lens helping transform potential failure points into opportunities for robust, scalable memory innovation.
(This article has been adapted and modified from content on Lam Research.)
