HomeNewsIndia NewsImec develops junction-less, gate-all-round, nanowire FETs

    Imec develops junction-less, gate-all-round, nanowire FETs

    nano-electronics research center

    At the 2016 Symposia on VLSI Technology & Circuits, nano-electronics research center imec presented gate-all-around (GAA) n- and p-MOSFET devices made of vertically stacked horizontal silicon (Si) nanowires (NWs) with a diameter of only 8-nm. The devices, which were fabricated on bulk Si substrates using an industry-relevant replacement metal gate (RMG) process, have excellent short-channel characteristics (SS = 65 mV/dec, DIBL = 42 mV/V for LG = 24 nm) at performance levels comparable to finFET reference devices. 

    GAA devices architectures offer optimal electrostatic control, thereby enabling ultimate CMOS device scaling. In addition, horizontal NWs are a natural extension of RMG finFETs, in contrast to vertical NWs which require more disruptive technology changes. Furthermore, stacking of NWs maximizes the drive current per footprint. Imec successfully combined these three aspects, and, for the first time, demonstrated vertically stacked horizontal Si NWs at scaled dimensions: 8-nm-diameter wires, 45-nm lateral pitch, and 20-nm vertical separation.

    Compared to the conventional bulk FinFET flow, imec implemented two major differences in the process flow. First, shallow trench isolation (STI) densification at 750°C resulted to preserve sharp silicon-germanium (SiGe)/Si interfaces, which is essential for well-controlled Si NW release. Second, a low-complexity ground plane doping scheme was applied, suppressing the bottom parasitic channel.  

    “By demonstrating stacked nanowires with solid electrostatic control, at scaled dimensions, and using an industry-relevant RMG process on bulk silicon substrates, imec has achieved breakthrough results that can pave the way to realizing sub-10nm technology nodes,” stated Dan Mocuta, Director Logic Device and Integration at imec. “The upcoming research phase will focus on achieving even denser pitches and on leveraging this knowledge to develop gate-all-around lateral nanowire CMOS devices.”

    Imec’s research into advanced logic scaling is performed in cooperation with imec’s key partners in its core CMOS programs including GlobalFoundries, Intel, Micron, SK Hynix, Samsung, TSMC, Huawei, Qualcomm and Sony.

    ELE Times Bureau
    ELE Times Bureauhttps://www.eletimes.ai/
    ELE Times provides a comprehensive global coverage of Electronics, Technology and the Market. In addition to providing in depth articles, ELE Times attracts the industry’s largest, qualified and highly engaged audiences, who appreciate our timely, relevant content and popular formats. ELE Times helps you build awareness, drive traffic, communicate your offerings to right audience, generate leads and sell your products better.

    LEAVE A REPLY

    Please enter your comment!
    Please enter your name here

    Related News

    Must Read

    What Are Memory Chips—and Why They Could Drive TV Prices Higher From 2026

    As the rupee continues to depreciate, crossing the magical...

    Anritsu & HEAD Launch Acoustic Evaluation Solution for Next-Gen Automotive eCall Systems

    ANRITSU CORPORATION and HEAD acoustics have jointly launched of...

    Dell Technologies’ 2026 Predictions: AI Acceleration, Sovereign AI & Governance

    Dell Technologies hosted its Predictions: 2026 & Beyond briefing...

    NAL-CSIR Advances Field testing of Indigenous Defence Tech

    The Council of Scientific and Industrial Research (CSIR)-National Aerospace...

    Toyota & NISE Test Mirai Hydrogen FCEV in India Conditions

    Toyota Kirloskar Motor (TKM) and the National Institute of...

    Nissan Powering EV Component Plant with Repurposed Batteries

    Nissan Australia has launched the Nissan Node project, a...

    KEC, Powernet & Wise Integration Co-Develop AI Server SMPS Power Solutions

    Wise Integration (France), Powernet (Korea) and KEC (Korea) will...

    FAMES Pilot Line R&D Advances: 400°C CMOS Enables 3D Integration Goals

    CEA-Leti, the coordinator of the FAMES Pilot line, has achieved...

    Keysight & KT SAT Nail Industry First GEO-to-LEO Multi-Orbit NTN Handover!

    Keysight Technologies, Inc., in collaboration with KT SAT, has...

    Nuvoton Emphasises Need to Strengthen Taiwan-Israel R&D Collaboration

    Nuvoton Technology showcased its leadership in international expansion by...