HomeTechnologyArtificial IntelligenceSilicon Portfolio, and oneAPI Software Expanded for Next-Gen. HPC

    Silicon Portfolio, and oneAPI Software Expanded for Next-Gen. HPC

    At the 2019 Supercomputing Conference (SC19), Intel shared plans to extend its leading portfolio of high performance computing (HPC) ready hardware, software, and development tools. With new product and initiative announcements made at the conference, Intel is easing the complexity of heterogeneous HPC computing deployments and artificial intelligence (AI) scenarios.

    oneAPI to simplify development and innovation

    Intel also shared details about its effort leading the oneAPI initiative. In the past, developer environments faced a great deal of complexity, like the requirement to manage multiple languages, tools, and code bases. With oneAPI, though, application developers gain an open and unified programming model that supports various compute engines, including Intel’s HPC-capable processors, accelerators and FPGAs. In addition, oneAPI offers developers new ways to build upon existing software investments using a single set of tools. Its code base also includes several optimizations to get the best performance on each architecture.

    The public beta of oneAPI development software offers provides a comprehensive portfolio of libraries, analysis tools, compilers, and assistants. Intel demonstrated further momentum for oneAPI by publishing v0.5 of the oneAPI specification which is now available on Intel DevCloud.

    With oneAPI’s alternative to the single-architecture, single-vendor programming environments commonly used today, developers have new ways to enable the growing trend of heterogeneous, multi-architecture HPC systems. 

    Ready for the exascale era

    Intel also spotlighted progress on Argonne National Laboratory’s Aurora exascale HPC system, expected to deploy in 2021. With the support of underlying Intel solutions, Aurora is expected to deliver a billion-billion calculations per second, making it one of the top HPC deployments in the nation.

    Aurora nodes will be comprised of two future 10nm-based Intel Xeon Scalable processors (code-named “Sapphire Rapids”) and six Ponte Vecchio HPC accelerators.

    When online, Aurora will feature many underlying Intel technologies. Argonne National Labs currently plans to incorporate tightly integrated nodes comprised of two future 10nm-based Intel Xeon Scalable processors (code-named “Sapphire Rapids”) and six Ponte Vecchio HPC accelerators. Supplemental technologies will include Xe architecture based HPC accelerators, Intel Optane DC Persistent Memory, and Intel’s Distributed Asynchronous Object Storage (DAOS) technology.

    Aurora will support over 230 petabytes of storage, and more than ten petabytes of memory. Slingshot fabric from Cray, a Hewlett Packard Enterprise Company, will accelerate data transfer among nodes dispersed across more than 200 racks.  Once all these technologies integrate into Aurora’s infrastructure, the system is expected to deliver performance levels about three times greater than the fastest system ranked on Top500.org’s current list.

    With the announcement of its latest technologies, Intel is helping usher in the exascale era to enable breakthroughs in science and industry.

    Intel accelerating the convergence of AI and HPC

    Intel Xeon processors currently support over 90 percent of the world’s fastest supercomputers listed among Top500.org’s latest rankings. At SC19, Intel outlined their efforts to expand their portfolio of HPC-ready processors, and add a new family of discrete accelerators, optimized for the convergence of HPC and AI.

    New “Ponte Vecchio” GPUs, based on Intel’s forthcoming Xe architecture, are highly flexible discrete general-purpose GPUs architected for HPC workloads like modeling, simulation, and AI training. Ponte Vecchio will be manufactured on Intel’s 7nm technology and will be Intel’s first Xe-based GPU optimized for HPC and AI workloads. Ponte Vecchio will leverage Intel’s Foveros 3D and embedded multi-die interconnect bridge (EMIB) packaging innovations and feature multiple technologies in-package, including high-bandwidth memory, Compute Express Link interconnect and other intellectual property.

    Intel also unveiled details around their next-generation Intel Xeon Scalable processors (code-named “Cooper Lake”) planned for release in the first half of 2020. 2nd Generation Intel Xeon Scalable processors are currently the only platform with both AI and HPC acceleration built-in. The new CPUs will expand on that capability by integrating new bfloat16 instructions to increase the accuracy of HPC models and further accelerate future AI breakthroughs.

    To learn more, visit: www.intel.com

    ELE Times Research Desk
    ELE Times Research Deskhttps://www.eletimes.ai
    ELE Times provides a comprehensive global coverage of Electronics, Technology and the Market. In addition to providing in depth articles, ELE Times attracts the industry’s largest, qualified and highly engaged audiences, who appreciate our timely, relevant content and popular formats. ELE Times helps you build awareness, drive traffic, communicate your offerings to right audience, generate leads and sell your products better.

    LEAVE A REPLY

    Please enter your comment!
    Please enter your name here

    Related News

    Must Read

    Optimized analog front-end design for edge AI

    Courtesy: Avnet Key Takeaways: 01.   AI models see data differently: what...

    Introducing Wi-Fi 8: The Next Boost for the Wireless AI Edge

    Courtesy: Broadcom Wi-Fi 8 has officially arrived—and it marks a...

    Vehicle to Grid (V2G) Charging in EVs: Understanding the Basics

    Much of the research around emerging technologies in Electric...

    Asia-Pacific Takes the Lead in AI Adoption Across Manufacturing

    Courtesy: Rockwell Automation Manufacturing around the world has undergone a...

    STMicroelectronics streamlines smart-home device integration with industry-first Matter NFC chip

    STMicroelectronics has unveiled a secure NFC chip designed to...

    Mitsubishi Electric India to Showcase Breakthrough Power Semiconductor Technologies at PCIM India 2025

    Mitsubishi Electric India, is set to introduce its flagship...

    ASMPT Wins New Orders for Nineteen Chip-to-Substrate TCB Tools to Serve AI Chip Market

    ASMPT announced it had won new orders for 19...

    Microchip Halves the Power Required to Measure How Much Power Portable Devices Consume

    Battery-operated devices and energy-restricted applications must track and monitor...