HomeDesignSystem-level PCB design environment updated

System-level PCB design environment updated

The focus of CR-8000 2018, according to the Zuken, is on enabling efficient front-loading of design constraints and specifications to the design creation process, coupled with sophisticated placement and routing capabilities for physical layout.

“With smart applications adding complexity to the product design process, controlling adherence of PCB designs to engineering and manufacturing specifications is a critical activity in advanced PCB design,” said Zuken chief strategy officer Humair Mandavia. “By providing more intelligent and automated features necessary to drive specification and communication of constraints and guidelines, Zuken wins back valuable time in the PCB design chain”, he added.

Front-loading of design intent from Design Gateway to Design Force has been achieved by adding a unified constraint browser for both applications, enabling hardware engineers to assign topology templates, modify differential signals and assign clearance classes to individual signals.

Using a rule stack editor during the circuit design phase, hardware engineers can now load design rules that include differential pair routing and routing width stacks directly from the design rule library into their schematic. Here they can modify and assign selected rules for cross talk and differential pair control.

An enhanced component browser enables component variants to be managed in the schematic, and assigned in a user-friendly table.

Manual routing is supported by an ‘auto complete and route’ function, and designers also have the option to look for paths on different layers while automatically inserting vias.

A new bus routing function allows paths to be sketched for multiple nets to be routed over dense areas. “An added benefit is the routing of individual signals to the correct signal length as per the hardware engineer’s front loaded constraints, to meet timing skew and budgets,” said the firm. If modifications to fully placed and routed boards are required, an automatic re-route function allows connected component pins to remain connected with a re-route operation during the move process.

Automatic stitching of vias in poured conductive areas can be specified by inside area on-line, perimeter outline or both inside and perimeter.

Design-for-manufacturing (DFM) has been enhanced to include checks for non-conductor items, such as silkscreen and assembly drawing placed reference designators. A design rule check will make sure component reference designators are listed in the same order as the parts for visual inspection accuracy.

 

ELE Times Research Desk
ELE Times Research Deskhttps://www.eletimes.ai
ELE Times provides a comprehensive global coverage of Electronics, Technology and the Market. In addition to providing in depth articles, ELE Times attracts the industry’s largest, qualified and highly engaged audiences, who appreciate our timely, relevant content and popular formats. ELE Times helps you build awareness, drive traffic, communicate your offerings to right audience, generate leads and sell your products better.

Related News

Must Read

STMicroelectronics Launches Next-Generation Ultralow-Power Image Sensors

STMicroelectronics, a global semiconductor leader serving customers across the...

Microchip Technology Launches Single-Pair Ethernet PHYs with Integrated Time and Security Functions

Microchip’s LAN878x and LAN888x PHY families enable secure, scalable...

Nuvoton Launches NuML Studio: Tool to Build and Deploy AI on Microcontrollers

Nuvoton Technology, a leading global semiconductor provider, has announced...

Rohde & Schwarz Presents its Advance Solutions for Power Electronics Testing at PCIM Expo 2026

Rohde & Schwarz presents its latest test and measurement solutions for...

Next-Gen Upgrade to the Halo Series, NoiseFit Halo 3 brings Presence-Led Design and AI to the Wrist

Noise, India’s leading connected lifestyle brand, announces the launch...

Keysight Expands PCIe 7.0 Test Portfolio with New Receiver Stress Calibration

Keysight Technologies today announces a new PCIe 7.0 Receiver...

VETH100A1DD1 ESD Protection Diode Passes IEEE 10BASE-T1S Compliance Tests

The Vishay Semiconductor VETH100A1DD1 ESD has successfully passed IEEE...