Xilinx on May 18, announced an achievement in PCI Express Gen4 capability. Together with IBM, the two companies are first to double interconnect performance between an accelerator and CPU through the use of PCI Express Gen4 compared to the existing widely-deployed PCI Express Gen3 standard. Gen4 doubles the bandwidth between CPUs and accelerators to 16 Gbps per lane, thereby accelerating performance in demanding data center applications such as artificial intelligence and data analytics.
Since the introduction of PCI Express in 2003, Xilinx has been a leader in PCI interconnect-based solutions, offering PCI Express compliance across its All Programmable FPGA families. IBM and Xilinx have achieved Gen4 interoperability between Xilinx 16nm UltraScale+ devices and IBM POWER9 processors, demonstrating the first-ever PCIe Gen4 capability in a programmable device.
“It’s clear the future of data center computing is going to be built on open standards,” said Bradley McCredie, vice president and Fellow at IBM. “This leadership in PCI Express is another reason that POWER architecture is being deployed in modern data centers.”
“We believe in open standards,” said Ivo Bolsens, CTO at Xilinx. “It’s gratifying to see this milestone between our companies that will alleviate significant performance bottlenecks in accelerated computing, particularly for data center computing.”
