One of the great challenges facing data communications is matching the silicon bandwidth with the face plate density. Today, switch silicon can process over 12 Tb/s. But getting this off the front panel at a reasonable density is a challenge. One direction is to move to faster Ethernet speeds. A great example of this is 400GE delivered by a QSFP-DD. By using 32 x QSFP-DD in a 1uI high switch we can deliver over 12Tb/s of bandwidth. Which provides a good match for current switch silicon.
This example is a good fit for ‘fat pipes’, like 400GE. But the reality is, much of today’s equipment may still only have 100GE ports. Of course, we can plug a QSFP28 into the QSFP-DD port to deliver a 100GE interface, but then you are throwing away a lot of bandwidth.
One technique to sidestep this is to use ‘breakout’ optics. For example, QSFP-DD using a DR4 PMD to bring out each 100G on a distinct fibre pair. They can be used as one pipe for 400G, or they can be used to deliver 4 x 100GE in a high density. This enables you to use the full switch bandwidth and a more mainstream Ethernet speed without losing any density.
The breakout application for QSFP-DD DR4 modules is far more demanding than the straight 400GE pipe. In fact, many new things need to be taken into consideration (as well as the capabilities of the switch silicon) including:
- Each of the 100GE streams must be distinct. That is, they can come from different sources with differing ppm clock offsets.
- The module must be able to manage 4 distinct optical power levels, LOS detect, etc. via its module management interface, typically over the I^2C using CMIS 4.0
- The 100GE must be suitably encoded. This is now 100GE on a single PAM-4 lambda, it needs a KP4 FEC and needs to be compatible with the host to module interface. There are 8 data lines, so with 4 x 100G we must use 2 lanes per 100G. Since each electrical lane uses PAM4 at 28Gbd, we are matched.
Client optic module companies have developed QSFP28 100GE modules which support this 100G/lambda optical interface while offering backwards compatibility with the ‘standard’ 100GE host. The module does the FEC encode/decode and manages the NRZ óPAM4 conversion. All this needs testing and validation. This is especially challenging to the PPM and skew offsets in timing around the QSFP-DD, and validation of the service disruption on the individual 100GE optical lanes.
We at VIAVI have developed a suite of powerful tools for our ONT family specifically designed to support breakout applications with complete coverage from the PHY layer all the way up to the Ethernet. This also includes specific tools for FEC stress and validation.
It is likely the high-density breakout will play an increasing role in pluggable optics as the processing capabilities of switch silicon keeps increasing. Already manufacturers have announced 25Tb/s capable silicon for this year and 800G class QSFP-DD modules are being developed to take advantage of 100G electrical lanes. The ability to test and validate breakout will continue to be an important part of a module development process.
